ASIC Digital Verification Engineer

We are looking for a skilled ASIC Digital Verification Engineer with experience in SoC-level verification for our Lidar and Photonic Products. This role focuses on building robust verification environments using SystemVerilog and UVM, targeting complex SoC designs for applications such as networking, display, and mixed-signal integration.

Key Responsibilities

Develop and maintain SystemVerilog-based verification environments for SoC-level and subsystem-level validation.

Implement UVM-based testbenches and verification components to simulate functional behavior.

Collaborate with design, architecture, and DV teams to ensure full functional coverage of digital IP blocks.

Create and execute directed and constrained-random test cases.

Analyze waveforms and debug simulation failures across RTL and gate-level simulations.

Automate test regressions and generate functional coverage reports.

Support IP and SoC integration with verification flow enhancements and reusable infrastructure.

Develop Python scripts for test automation and data management.

Qualifications

Bachelor’s or Master’s degree in Electrical or Computer Engineering.

4+ years of hands-on experience in ASIC digital verification.

Strong knowledge of SystemVerilog, UVM, and digital design concepts.

Experience verifying SoC-level designs, including bus protocols, peripherals, and memory interfaces.

Background in networking, display, or mixed-signal SoC designs is a strong plus.

Proficiency in Python scripting for test automation and tooling.

Familiarity with industry-standard simulation tools (e.g., Synopsys VCS, Cadence Xcelium, Siemens Questa).

Excellent debugging and communication skills.

Be sure to include the position applying for, your resume, experience, education, and interest in your email.

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